This invention relates to microprogrammable microprocessors, and more particularly to ROM based microprogrammable microprocessors, and a Universal Serial Bus (xe2x80x9cUSBxe2x80x9d) microcontroller development system configured to aid-in the design, debug, and testing of USB compliant devices and firmware using a ROM based microprogrammable microprocessor.
Microprocessor instruction sets are well known in the art. The instruction set of a microprocessor consists of a set of instructions recognized by the microprocessor. Each instruction recognized by the microprocessor is defined in an instruction architectural specification which defines the useful function performed by each instruction and a sequence of actions required to be performed by the microprocessor in order to carry out the instruction. Each instruction in the instruction set is encoded to identify the specific sequence of actions defined by the instruction architectural specification for that instruction.
With the definition of an instruction architectural specification and the encoding of each instruction thereby defined, the microprocessor then has the task of identifying and performing the sequence of actions required to carry out each instruction, thereby implementing the instruction set.
Typically, instruction sets are implemented in either ROM or a set of logic gates. The tradeoff between ROM based instruction sets and gate implementations is the speed at which instructions are retrieved versus the flexibility of implementing new or modified instruction sets. Gate based instruction sets are faster than ROM implementations, but ROM based sets are microprogrammable which makes updating an instruction set as simple as changing the values stored in the ROM.
In many implementations of microprocessors, the interpretation of an instruction byte is performed by combinatorial logic to generate several output terms, each of which gate logic/hardware resources such as Arithmetic Logic Units (xe2x80x9cALUsxe2x80x9d) and register files. The disadvantage to this approach is that any change in hardware resources or instruction encoding will require redesign and relayout of the combinatorial logic.
FIG. 4 shows a conventional approach to this problem which is to use a read only memory ROM 21 to store the mapping from instruction to decode outputs. For 8 bits of instruction and 15 steps per instruction, mapping requires 28 plus 24 bits of addressing or 4K words, each of which words needs to be as wide as needed to control all the resources. For the microprocessor described herein, this width is 16 bits.
A 4Kxc3x9716 bit memory can occupy a significant area, and in most technologies this size is larger than the hardware resources it is controlling. This same mapping if synthesized to random gates would be more area efficient, but would suffer from the previously mentioned problem. A method is needed to provide adequate storage for ROM based instructions, but reduce the bit storage requirement for those instructions, thereby making ROM based instruction decoding more size and cost efficient.
Any electronic device utilizing ROM based instruction sets needs to have adequate ROM storage for those instructions. ROM based instruction sets are more size and cost efficient if the amount of ROM storage needed to implement the instruction set can be reduced.
USB is a peripheral bus standard that allows computer peripherals to be attached to a personal computer without the need for specialized cards or other vendor specific hardware attachments. The USB standard specifies a common configuration for the connection of well known peripherals such as CD-ROM, tape and floppy disk drives, scanners, printers, keyboards, joysticks, mice, telephones, modems, etc. In addition to well known peripheral devices, the USB standard has flexibility to accommodate less known and newly developed technologies. Information about the USB standard, including the specification for building USB compliant devices, is currently available free of charge over the Internet.
Developers wishing to implement USB devices must build that device to the USB standard. Prior to fabricating IC""s for USB standard devices, a developer will spend a significant amount of resources in testing and refinement of prototypes. An efficient method for testing USB compliant devices is needed to reduce the costs associated with prototype development and testing of those devices.
The design and manufacture of electronic devices such as counters, state machines, specialized registers, and microprocessors is currently aided by technologies that allow engineers to specify design characteristics of a circuit, such as storage device size, register types, connections and associated logic, in a Hardware Description Language (xe2x80x9cHDLxe2x80x9d). This source code or HDL is then compiled, allowing the electronic device to be simulated and debugged while implementing the specified circuit characteristics. Once the operation of a device is verified, the compiled source code can be mapped to a specific architecture such as Application Specific Integrated Circuits (xe2x80x9cASICsxe2x80x9d) or Field Programmable Gate Arrays (xe2x80x9cIFPGAsxe2x80x9d). This allows the system designer to produce a device with design flexibility and portability into various architecture families.
As an example, a 3-bit shift register can be implemented in a HDL such as Register Transfer Language (xe2x80x9cRTLxe2x80x9d) with the following RTL statements:
ENTITY shifter3 IS port (
clk: IN BIT;
x: IN BIT;
q0: OUT BIT;
q1: OUT BIT;
q2: OUT BIT;
END shifter3;
ARCHITECTURE struct OF shifter3 IS
SIGNAL q0_temp, q1_temp, q2_temp: BIT;
BEGIN
d1: DFF PORT MAP (x,clk,q0_temp);
d2: DFF PORT MAP (q0_temp,clk,q1_temp);
d3: DFF PORT MAP (q1_temp,clk,q2_temp);
q0  less than =q0_temp;
q1  less than =q1_temp;
q2  less than =q2_temp;
END struct;
which defines the inputs and outputs of the shifter and then maps those bits to a series of D Flip-Flops. After compiling the source code and debugging the circuit, a netlist can be generated for a specific family of FPGA or ASIC devices to produce the circuit with the desired functionality.
Accordingly, one object of the present invention is to provide a ROM based microprocessor instruction set implemented in a novel fashion that reduces the required amount of ROM storage needed to implement an instruction set. This is done by providing a microprocessor with an instruction set that is microprogrammable, utilizing 2 ROMs in which the first ROM contains an address look-up table and the second ROM contains re-usable subroutines that perform operations implementing the instruction set. The result is a dual ROM microprogrammable microprocessor that utilizes subroutines in more than one instruction, thereby conserving system resources.
Another object of the present invention is to provide a Universal Serial Bus (xe2x80x9cUSBxe2x80x9d) microcontroller development system utilizing a dual ROM microprogrammable microprocessor. The microcontroller includes a dual ROM microprogrammable microprocessor with instruction RAM, a controller with a computer interface (e.g., RS-232) to a personal computer or other external computing device, data RAM, USB logic and registers for interfacing to a USB host computer, and I/O logic and registers for interfacing to an I/O device. The USB microcontroller development system includes the microcontroller, an external computer, a USB host computer, and an I/O device. The USB microcontroller development system allows both the dual ROM microprogrammable microprocessor or an attached external computer to control the microcontroller. This is accomplished by mapping the USB microcontroller system state which includes the contents of the data RAM, the dual ROM microprogrammable microprocessor""s system state registers including system state registers corresponding to the contents of the instruction RAM, the USB logic registers, and the I/O logic registers to a system bus. The controller or dual ROM microprogrammable microprocessor places address, data, and control signals on the system bus which are decoded by various logic to allow reading or writing of the system state. The controller reads or writes the instruction RAM by reading or writing a program counter and an instruction register, included as part of the dual ROM microprogrammable microprocessor""s system state registers, via the system bus. Accordingly, the external computer connected to the controller via the RS-232 bus can read or write the USB microcontroller system state to aid in the design, debug, and testing of USB compliant devices and firmware.
It is also an object of the present invention to provide a development access device on the external computer for providing a user a graphical interface for controlling the USB microcontroller. The development access device displaying menus, buttons, text boxes etc., corresponding to the dual ROM microprogrammable microprocessor""s system state registers, the contents of the instruction RAM, the USB logic registers, and the I/O logic registers. The user, after selecting the appropriate menu, button, or filling in the appropriate text box, can read or write the corresponding dual ROM microprogrammable microprocessor""s system state registers, the contents of the instruction RAM, the USB logic registers, and the I/O logic registers via the external computer and computer interface to control the USB microcontroller.
It is yet another object of the present invention is to provide a method of implementing a dual ROM instruction set in a microprogrammable microprocessor having a first ROM storing a plurality of subroutine starting address sets each set corresponding to a program instruction, a second ROM storing a plurality of subroutines each subroutine containing a series of microprogram instructions, and sequencer logic configured to sequence each subroutine of the plurality of subroutines in accordance with a program instruction.
It is another object of the present invention to provide a method for implementing the above USB microcontroller development system utilizing a Hardware Description Language. By utilizing a Hardware Description Language, the design engineers are free to concentrate on the design of important features of the system and it""s functionality rather than a gate level implementation of the system. After determining top level characteristics and functional blocks of the system, an HDL program describing those characteristics and functional blocks is developed and debugged. In the present invention, HDL implemented processes are used in designing various functional blocks of the USB microcontroller development system. The USB microcontroller development system designed using HDL is then mapped to FPGAs and packaged onto a single printed circuit board along with minimal additional logic such as EEPROMs and RAM.
The above and other objects are achieved according to the present invention by providing a new and improved microprogrammable microprocessor having a dual ROM instruction set including a first ROM storing a plurality of microprogram subroutine starting address sets, each set containing at least one subroutine starting address and corresponding to a program instruction; a second ROM storing a plurality of subroutines, each subroutine containing a series of microprogram instructions; and sequencer logic coupled to the first ROM and to the second ROM and configured to initiate the retrieval of subroutine starting addresses from the first ROM and to sequence subroutines in the second ROM corresponding to the subroutine starting addresses retrieved; wherein the second ROM outputs the microprogram instructions to an arithmetic logic unit to carry out the microprogram instructions.
According to a second aspect of the present invention, a microcontroller is provided including a system bus; a microprogrammable microprocessor coupled to the system bus and configured to transfer data and control signals over the system bus and having a dual ROM instruction set including a first ROM storing a plurality of microprogram subroutine starting address sets, each set containing at least one subroutine starting address and corresponding to a program instruction, a second ROM storing a plurality of subroutines, each subroutine containing a series of microprogram instructions, and sequencer logic coupled to the first ROM and to the second ROM and configured to initiate the retrieval of subroutine starting addresses from the first ROM and to sequence subroutines in the second ROM corresponding to the subroutine starting addresses retrieved, wherein the second ROM outputs the microprogram instructions to an arithmetic logic unit to carry out the microprogram instructions; a memory device coupled to the microprogrammable microprocessor and mapped to the system bus and configured to store microprogram instructions for execution by the microprogrammable microprocessor; a controller coupled to the system bus and configured to transfer data and control signals to the microprogrammable microprocessor over the system bus; a host interface coupled to the system bus and configured to interface to a host computer and receive the data and the control signals over the system bus from the microprogrammable microprocessor; and an I/O interface coupled to the system bus and configured to interface to at least one I/O device and receive the data and the control signals over the system bus from the microprogrammable microprocessor.
According to a third aspect of the present invention, a method of implementing a dual RON instruction set in a microprogrammable microprocessor having a first ROM and a second ROM, and includes the steps of (A) storing a plurality of subroutine starting address sets each set corresponding to a program instruction in the first RON, and one or more subroutines each subroutine containing one or more microprogram instructions in the second ROM; (B) retrieving a subroutine starting address set corresponding to a program instruction from the first ROM; and (C) sequencing a series of microprogram instructions in the second RON for each subroutine identified in the subroutine starting address set, thereby executing a program instruction.
According to a fourth aspect of the present invention, a method of fabricating a microprogrammable microprocessor with a dual ROM instruction set includes determining a set of functional requirements for a dual ROM instruction set including a first ROM for storing subroutine starting addresses, a second ROM for containing microprogram subroutines, a sequencer for providing timing and control signals for retrieval of subroutine starting addresses and sequencing of microprogram subroutines; determining a set of functional microprocessor requirements to operate in conjunction with the dual ROM instruction set and specifying a microprogrammable microprocessor with at least two electronic elements; defining the set of functional microprocessor requirements and the functional requirements of the control circuit in a Hardware Description Language (HDL); compiling the HDL language to derive a circuit representation of the microcontroller development system;
and mapping the circuit representation onto one or more devices.